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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-12614-2E
8-bit Proprietary Microcontrollers
CMOS
F2MC-8FX MB95100AM Series
MB95108AM/F104AMS/F104ANS/F104AJS/F106AMS/F106ANS/F106AJS/ MB95F108AMS/F108ANS/F108AJS/F104AMW/F104ANW/F104AJW/F106AMW/ MB95F106ANW/F106AJW/F108AMW/F108ANW/F108AJW/FV100D-103
DESCRIPTION
The MB95100AM series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions. Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
FEATURE
* F2MC-8FX CPU core Instruction set optimized for controllers * Multiplication and division instructions * 16-bit arithmetic operations * Bit test branch instruction * Bit manipulation instructions etc. * Clock * Main clock * Main PLL clock * Sub clock (for dual clock product) * Sub PLL clock (for dual clock product) (Continued)
Be sure to refer to the "Check Sheet" for the latest cautions on development.
"Check Sheet" is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html "Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development.
Copyright(c)2006 FUJITSU LIMITED All rights reserved
MB95100AM Series
(Continued) * Timer * 8/16-bit compound timer x 2 channels * 16-bit reload timer * 8/16-bit PPG x 2 channels * 16-bit PPG x 2 channels * Timebase timer * Watch prescaler (for dual clock product) * LIN-UART * Full duplex double buffer * Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable * UART/SIO * Full duplex double buffer * Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable * I2C* Built-in wake-up function * External interrupt * Interrupt by edge detection (rising, falling, or both edges can be selected) * Can be used to recover from low-power consumption (standby) modes. * 8/10-bit A/D converter * 8-bit or 10-bit resolution can be selected * Low-power consumption (standby) mode * Stop mode * Sleep mode * Watch mode (for dual clock product) * Timebase timer mode * I/O ports : * The number of maximum ports * Single clock product : 54 ports * Dual clock product : 52 ports * Port configuration * General-purpose I/O ports (N-ch open drain) : 6 ports * General-purpose I/O ports (CMOS) : Single clock product : 48 ports Dual clock product : 46 ports * Programmable input voltage levels of port Automotive input level / CMOS input level / hysteresis input level * Flash memory security function Protects the content of Flash memory (Flash memory device only) * : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips.
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MB95100AM Series
MEMORY LINEUP
Flash MB95F104AMS/F104ANS/F104AJS MB95F104AMW/F104ANW/F104AJW MB95F106AMS/F106ANS/F106AJS MB95F106AMW/F106ANW/F106AJW MB95F108AMS/F108ANS/F108AJS MB95F108AMW/F108ANW/F108AJW 16K bytes 32K bytes 60K bytes RAM 512 bytes 1K byte 2K bytes
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MB95100AM Series
PRODUCT LINEUP
Part number MB95 108AM Parameter Type ROM capacity*1 RAM capacity*1 Reset output Clock system Low voltage detection reset Clock supervisor Selectable single/dual clock*3 Yes/No Yes Single clock Dual clock MASK ROM product MB95F 104AMS/ MB95F 106AMS/ MB95F 108AMS MB95F 104ANS/ MB95F 106ANS/ MB95F 108ANS MB95F 104AMW/ MB95F 106AMW/ MB95F 108AMW MB95F 104ANW/ MB95F 106ANW/ MB95F 108ANW MB95F 104AJS/ MB95F 106AJS/ MB95F 108AJS MB95F 104AJW/ MB95F 106AJW/ MB95F 108AJW
Flash memory product 60 Kbytes (Max) 2 Kbytes (Max) No Single clock Dual clock
Option*2
No
Yes No
No
Yes Yes
CPU functions
Number of basic instructions : 136 Instruction bit length : 8 bits Instruction length : 1 to 3 bytes Data bit length : 1, 8, and 16 bits Minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25 MHz) Interrupt processing time : 0.6 s (at machine clock frequency 16.25 MHz) * Single clock product : 54 ports (N-ch open drain : 6 ports, CMOS : 48 ports) * Dual clock product : 52 ports (N-ch open drain : 6 ports, CMOS : 46 ports) Programmable input voltage levels of port : Automotive input level / CMOS input level / hysteresis input level Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz) Reset generated cycle At main oscillation clock 10 MHz : Min 105 ms At sub oscillation clock 32.768 kHz (for dual clock product) : Min 250 ms Capable of replacing 3 bytes of ROM data Master/slave sending and receiving Bus error function and arbitration function Detecting transmitting direction function Start condition repeated generation and detection functions Built-in wake-up function Data transfer capable in UART/SIO Full duplex double buffer, variable data length (5/6/7/8-bit), built-in baud rate generator NRZ type transfer format, error detected function LSB-first or MSB-first can be selected. Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable (Continued)
General-purpose I/O ports Timebase timer Peripheral functions 4 Watchdog timer Wild register
I2C
UART/SIO
MB95100AM Series
Part number MB95 108AM Parameter
MB95F 104AMS/ MB95F 106AMS/ MB95F 108AMS
MB95F MB95F MB95F 104ANS/ 104AMW/ 104ANW/ MB95F MB95F MB95F 106ANS/ 106AMW/ 106ANW/ MB95F MB95F MB95F 108ANS 108AMW 108ANW
MB95F 104AJS/ MB95F 106AJS/ MB95F 108AJS
MB95F 104AJW/ MB95F 106AJW/ MB95F 108AJW
LIN-UART
Dedicated reload timer allowing a wide range of communication speeds to be set. Full duplex double buffer Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable LIN functions available as the LIN master or LIN slave.
8/10-bit A/D converter 8-bit or 10-bit resolution can be selected. (12 channels) Two clock modes and two counter operating modes can be selected. Square waveform output Count clock : 7 internal clocks and external clock can be selected. Counter operating mode : reload mode or one-shot mode can be selected. Each channel of the timer can be used as "8-bit timer x 2 channels" or "16-bit timer x 1 channel". Built-in timer function, PWC function, PWM function, capture function, and square waveform output Count clock : 7 internal clocks and external clock can be selected PWM mode or one-shot mode can be selected. Counter operating clock : 8 selectable clock sources Support for external trigger start Each channel of the PPG can be used as "8-bit PPG x 2 channels" or "16-bit PPG x 1 channel". Counter operating clock : Eight selectable clock sources
16-bit reload timer
Peripheral functions
8/16-bit compound timer (2 channels)
16-bit PPG (2 channels) 8/16-bit PPG (2 channels)
Count clock : 4 selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s) Watch counter Counter value can be set from 0 to 63. (Capable of counting for 1 minute when (for dual clock product) selecting clock source 1 second and setting counter value to 60) Watch prescaler 4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s) (for dual clock product) External interrupt (12 channels) Interrupt by edge detection (rising, falling, or both edges can be selected.) Can be used to recover from standby modes. Supports automatic programming, Embedded AlgorithmTM *4 Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Number of write/erase cycles (Minimum) : 10000 times Data retention time : 20 years Erase can be performed on each block Block protection with external programming voltage Flash Security Feature for protecting the content of the Flash (MB95F108AMS/F108ANS/F108AJS/F108AMW/F108ANW/F108AJW only) Sleep, stop, watch (for dual clock product) , and timebase timer (Continued)
Flash memory
Standby mode
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MB95100AM Series
(Continued) *1 : For ROM capacity and RAM capacity, refer to " MEMORY LINEUP". *2 : For details of option, refer to " MASK OPTION". *3 : Specify clock mode when ordering MASK ROM. *4 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc. Note : Part number of the evaluation product in MB95100AM series is MB95FV100D-103. When using it, the MCU board (MB2146-303A) is required.
6
MB95100AM Series
OSCILLATION STABILIZATION WAIT TIME
The initial value of the main clock oscillation stabilization wait time is fixed to the maximum value. The maximum value is shown as follows. Oscillation stabilization wait time (2 -2) /FCH
14
Remarks Approx. 4.10 ms (at main oscillation clock 4 MHz)
PACKAGES AND CORRESPONDING PRODUCTS
Part number MB95F104AMS/F104ANS/ F104AJS MB95F106AMS/F106ANS/ MB95108AM F106AJS MB95F108AMS/F108ANS/ F108AJS MB95F104AMW/F104ANW/ F104AJW MB95F106AMW/F106ANW/ MB95FV100D-103 F106AJW MB95F108AMW/F108ANW/ F108AJW
Parameter FPT-64P-M03 FPT-64P-M09 BGA-224PM08 : Available : Unavailable
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MB95100AM Series
DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS
* Notes on Using Evaluation Products The Evaluation product has not only the functions of the MB95100AM series but also those of other products to support software development for multiple series and models of the F2MC-8FX family. The I/O addresses for peripheral resources not used by the MB95100AM series are therefore access-barred. Read/write access to these access-barred addresses may cause peripheral resources supposed to be unused to operate, resulting in unexpected malfunctions of hardware or software. Particularly, do not use word access to odd numbered byte address in the prohibited areas (If these access are used, the address may be read or write unexpectedly) . Also, as the read values of prohibited addresses on the evaluation product are different to the values on the flash memory and MASK ROM products, do not use these values in the program. The Evaluation product do not support the functions of some bits in single-byte registers. Read/write access to these bits does not cause hardware malfunctions. Since the Evaluation, Flash memory, and MASK ROM products are designed to behave completely the same way in terms of hardware and software. * Difference of Memory Spaces If the amount of memory on the Evaluation product is different from that of the Flash memory or MASK ROM product, carefully check the difference in the amount of memory from the model to be actually used when developing software. For details of memory space, refer to " CPU CORE". * Current Consumption The current consumption of Flash memory product is typically greater than for MASK ROM product. For details of current consumption, refer to " ELECTRICAL CHARACTERISTICS". * Package For details of information on each package, refer to " PACKAGES AND CORRESPONDING PRODUCTS" and " PACKAGE DIMENSIONS". * Operating Voltage The operating voltage are different among the Evaluation, Flash memory, and MASK ROM products. For details of operating voltage, refer to " ELECTRICAL CHARACTERISTICS". * Difference between RST and MOD Pins The RST and MOD pins are hysteresis inputs on the MASK ROM product. A pull-down resistor is provided for the MOD pin of the MASK ROM product.
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MB95100AM Series
PIN ASSIGNMENT
(TOP VIEW)
AVss P30/AN00 P31/AN01 P32/AN02 P33/AN03 P34/AN04 P35/AN05 P36/AN06 P37/AN07 P40/AN08 P41/AN09 P42/AN10 P43/AN11 P67/SIN P66/SOT P65/SCK 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVcc AVR PE3/INT13 PE2/INT12 PE1/INT11 PE0/INT10 P83 P82 P81 P80 P71/TI0 P70/TO0 MOD X0 X1 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P64/EC1 P63/TO11 P62/TO10 P61/PPG11 P60/PPG10 P53/TRG1 P52/PPG1 P51/SDA0 P50/SCL0 P24/EC0 P23/TO01 P22/TO00 P21/PPG01 P20/PPG00 P14/PPG0 P13/TRG0/ADTG
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Vcc C PG2/X1A PG1/X0A RST P00/INT00 P01/INT01 P02/INT02 P03/INT03 P04/INT04 P05/INT05 P06/INT06 P07/INT07 P10/UI0 P11/UO0 P12/UCK0
(FPT-64P-M03, FPT-64P-M09) * : Single clock product is general-purpose port, and dual clock product is sub clock oscillation pin.
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MB95100AM Series
PIN DESCRIPTION
Pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Pin name AVcc AVR PE3/INT13 PE2/INT12 PE1/INT11 PE0/INT10 P83 P82 P81 P80 P71/TI0 H P70/TO0 MOD X0 X1 Vss Vcc C PG2/X1A H/A PG1/X0A RST P00/INT00 P01/INT01 P02/INT02 P03/INT03 P04/INT04 P05/INT05 P06/INT06 P07/INT07 P10/UI0 G General-purpose I/O port. The pin is shared with UART/SIO ch.0 data input. (Continued) 10 C General-purpose I/O port. The pins are shared with external interrupt input. Large current port. B' B A General-purpose I/O port. The pin is shared with 16-bit reload timer ch.0 output. General-purpose I/O port. The pin is shared with 16-bit reload timer ch.0 input. An operating mode designation pin Main clock input oscillation pin Main clock input/output oscillation pin Power supply pin (GND) Power supply pin Capacitor connection pin Single clock product is general-purpose port (PG2) . Dual clock product is sub clock input/output oscillation pin (32 kHz). Single clock product is general-purpose port (PG1) . Dual clock product is sub clock input oscillation pin (32 kHz). Reset pin O General-purpose I/O port P General-purpose I/O port. The pins are shared with the external interrupt input. I/O Circuit type* Function A/D converter power supply pin A/D converter reference input pin
MB95100AM Series
Pin no. 31 32
Pin name P11/UO0 P12/UCK0 P13/TRG0/ ADTG P14/PPG0 P20/PPG00 P21/PPG01 P22/TO00 P23/TO01 P24/EC0 P50/SCL0
I/O Circuit type*
Function General-purpose I/O port. The pin is shared with UART/SIO ch.0 data output. General-purpose I/O port. The pin is shared with UART/SIO ch.0 clock I/O.
H
33
General-purpose I/O port. The pin is shared with 16-bit PPG ch.0 trigger input (TRG0) and A/D trigger input (ADTG). General-purpose I/O port. The pin is shared with 16-bit PPG ch.0 output. General-purpose I/O port. The pins are shared with 8/16-bit PPG ch.0 output.
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
H
General-purpose I/O port. The pins are shared with 8/16-bit compound timer ch.0 output. General-purpose I/O port. The pin is shared with 8/16-bit compound timer ch.0 clock input. General-purpose I/O port. The pin is shared with I2C ch.0 clock I/O. General-purpose I/O port. The pin is shared with I2C ch.0 data I/O. General-purpose I/O port. The pin is shared with 16-bit PPG ch.1 output. General-purpose I/O port. The pin is shared with 16-bit PPG ch.1 trigger input. General-purpose I/O port. The pins are shared with 8/16-bit PPG ch.1 output. General-purpose I/O port. The pins are shared with 8/16-bit compound timer ch.1 output.
I P51/SDA0 P52/PPG1 H P53/TRG1 P60/PPG10 P61/PPG11 P62/TO10 P63/TO11 P64/EC1 P65/SCK P66/SOT P67/SIN P43/AN11 P42/AN10 P41/AN09 P40/AN08 J L K
General-purpose I/O port. The pin is shared with 8/16-bit compound timer ch.1 clock input. General-purpose I/O port. The pin is shared with LIN-UART clock I/O. General-purpose I/O port. The pin is shared with LIN-UART data output. General-purpose I/O port. The pin is shared with LIN-UART data input.
General-purpose I/O port. The pins are shared with A/D converter analog input.
(Continued) 11
MB95100AM Series
(Continued) Pin no. 56 57 58 59 60 61 62 63 64 Pin name P37/AN07 P36/AN06 P35/AN05 P34/AN04 P33/AN03 P32/AN02 P31/AN01 P30/AN00 AVss A/D converter power supply pin (GND) J General-purpose I/O port. The pins are shared with A/D converter analog input. I/O Circuit type* Function
*: For the I/O circuit type, refer to " I/O CIRCUIT TYPE"
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MB95100AM Series
I/O CIRCUIT TYPE
Type Circuit Clock input
X1 (X1A)
Remarks * Oscillation circuit * High-speed side Feedback resistance : approx. 1 M * Low-speed side Feedback resistance : approx. 10 M
A
X0 (X0A)
N-ch
Standby control * Only for input Hysteresis input only for MASK ROM product With pull-down resistor only for MASK ROM product * Hysteresis input only for MASK ROM product * Reset output * CMOS output * Hysteresis input * Automotive input
Mode input B
R
B'
N-ch
Reset input Reset output
P-ch
Digital output Digital output
N-ch
C Standby control External interrupt enable
R P-ch P-ch
Hysteresis input Automotive input
Pull-up control Digital output Digital output CMOS input Hysteresis input
G
* * * * *
CMOS output CMOS input Hysteresis input With pull-up control Automotive input
N-ch
Standby control
Automotive input (Continued)
13
MB95100AM Series
Type
R P-ch
Circuit Pull-up control
P-ch
Remarks * * * * CMOS output Hysteresis input With pull-up control Automotive input
Digital output Digital output
H
N-ch
Hysteresis input Standby control Automotive input * * * * N-ch open drain output CMOS input Hysteresis input Automotive input
N-ch
Digital output CMOS input Hysteresis input Automotive input
I
Standby control
R P-ch P-ch
Pull-up control Digital output Digital output Analog input Hysteresis input
* * * * *
CMOS output Hysteresis input Analog input With pull-up control Automotive input
J
N-ch
A/D control Standby control
P-ch
Automotive input * CMOS output * Hysteresis input * Automotive input
Digital output Digital output Hysteresis input
K
N-ch
Standby control
Automotive input (Continued)
14
MB95100AM Series
(Continued) Type
Circuit
P-ch
Remarks Digital output Digital output CMOS input Hysteresis input Automotive input * N-ch open drain output * Hysteresis input * Automotive input * * * * CMOS output CMOS input Hysteresis input Automotive input
N-ch
L
Standby control
N-ch
Digital output Hysteresis input
O Standby control
Automotive input
R P-ch P-ch
Pull-up control Digital output Digital output Hysteresis input Automotive input
* * * *
CMOS output Hysteresis input With pull-up control Automotive input
P
N-ch
Standby control External interrupt control
15
MB95100AM Series
HANDLING DEVICES
* Preventing Latch-up Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used. Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between VCC pin and VSS pin. When latch-up occurs, power supply current increases rapidly and might thermally damage elements. Also, take care to prevent the analog power supply voltage (AVCC, AVR) and analog input voltage from exceeding the digital power supply voltage (VCC) when the analog system power supply is turned on or off. * Stable Supply Voltage Supply voltage should be stabilized. A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range of the Vcc power-supply voltage. For stabilization, in principle, keep the variation in Vcc ripple (p-p value) in a commercial frequency range (50 Hz/60 Hz) not to exceed 10% of the standard Vcc value and suppress the voltage variation so that the transient variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched. * Precautions for Use of External Clock Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from sub clock mode or stop mode.
PIN CONNECTION
* Treatment of Unused Input Pin Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 k. Any unused input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins. If there is unused output pin, make it to open. * Treatment of Power Supply Pins on A/D Converter Connect to be AVCC = VCC and AVSS = AVR = VSS even if the A/D converter is not in use. Noise riding on the AVCC pin may cause accuracy degradation. So, connect approx. 0.1 F ceramic capacitor as a bypass capacitor between AVCC and AVSS pins in the vicinity of this device. * Power Supply Pins In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 F between VCC and VSS near this device.
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MB95100AM Series
* Mode Pin (MOD) Connect the MOD pin directly to VCC or VSS pins. To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to minimize the distance from the MOD pins to VCC or VSS pins and to provide a low-impedance connection. Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of VCC pin must have a capacitance value higher than CS. For connection of smoothing capacitor CS, refer to the diagram below. * C pin connection diagram
C
CS
* Analog Power Supply Always set the same potential to AVCC and VCC pins. When VCC > AVCC, the current may flow through the AN00 to AN11 pins.
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MB95100AM Series
PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL PROGRAMMER
* Supported Parallel Programmers and Adapters The following table lists supported parallel programmers and adapters. Package Applicable adapter model FPT-64P-M03 FPT-64P-M09 TEF110-108F35AP TEF110-108F36AP Parallel programmers AF9708 (Ver 02.35G or more) AF9709/B (Ver 02.35G or more) AF9723+AF9834 (Ver 02.08E or more)
Note : For information on applicable adapter models and parallel programmers, contact the following: Flash Support Group, Inc. TEL: +81-53-428-8380 * Sector Configuration The individual sectors of Flash memory correspond to addresses used for CPU access and programming by the parallel programmer as follows: * MB95F108AMS/F108ANS/F108AJS/F108AMW/F108ANW/F108AJW (60 Kbytes) Flash memory SA1 (4 Kbytes) SA2 (4 Kbytes) 2FFFH 3000H SA3 (4 Kbytes) 3FFFH 4000H SA4 (16 Kbytes) 7FFFH 8000H SA5 (16 Kbytes) BFFFH C000H SA6 (4 Kbytes) CFFFH D000H SA7 (4 Kbytes) DFFFH E000H SA8 (4 Kbytes) EFFFH F000H SA9 (4 Kbytes) FFFFH 7FFFFH *: Programmer addresses are equivalent to CPU addresses, used when the parallel programmer programs data into Flash memory. These programmer addresses are used for the parallel programmer to program or erase data in Flash memory. * Programming Method 1) Set the type code of the parallel programmer to "17222". 2) Load program data to programmer addresses 71000H to 7FFFFH. 3) Programmed by parallel programmer 18 7EFFFH 7F000H 7DFFFH 7E000H 7CFFFH 7D000H 7BFFFH 7C000H
Upper bank Lower bank
CPU address 1000H 1FFFH 2000H
Programmer address* 71000H 71FFFH 72000H 72FFFH 73000H 73FFFH 74000H 77FFFH 78000H
MB95100AM Series
* MB95F106AMS/F106ANS/F106AJS/F106AMW/F106ANW/F106AJW (32 Kbytes) Flash memory SA5 (16 Kbytes) BFFFH C000H SA6 (4 Kbytes) CFFFH D000H SA7 (4 Kbytes) DFFFH E000H SA8 (4 Kbytes) EFFFH F000H SA9 (4 Kbytes) FFFFH 7FFFFH *: Programmer addresses are equivalent to CPU addresses, used when the parallel programmer programs data into Flash memory. These programmer addresses are used for the parallel programmer to program or erase data in Flash memory. * Programming Method 1) Set the type code of the parallel programmer to "17222" 2) Load program data to programmer addresses 78000H to 7FFFFH. 3) Programmed by parallel programmer * MB95F104AMS/F104ANS/F104AJS/F104AMW/F104ANW/F104AJW (16 Kbytes) Flash memory SA6 (4 Kbytes) CFFFH D000H SA7 (4 Kbytes) DFFFH E000H SA8 (4 Kbytes) EFFFH F000H SA9 (4 Kbytes) FFFFH 7FFFFH *: Programmer addresses are equivalent to CPU addresses, used when the parallel programmer programs data into Flash memory. These programmer addresses are used for the parallel programmer to program or erase data in Flash memory. * Programming Method 1) Set the type code of the parallel programmer to "17222" 2) Load program data to programmer addresses 7C000H to 7FFFFH. 3) Programmed by parallel programmer 19 7EFFFH 7F000H 7DFFFH 7E000H 7CFFFH 7D000H CPU address C000H Programmer address* 7C000H 7EFFFH 7F000H 7DFFFH 7E000H 7CFFFH 7D000H 7BFFFH 7C000H CPU address 8000H Programmer address* 78000H
MB95100AM Series
BLOCK DIAGRAM
F MC-8FX CPU RST X0,X1 PG2/X1A* PG1/X0A* Reset control Clock control Watch prescaler Watch counter P00/INT00 to P07/INT07 P10/UI0 P11/UO0 P12/UCK0 16-bit PPG ch.0
Internal bus
External interrupt ch.0 to ch.7
2
ROM RAM Interrupt control Wild register
8/16-bit PPG ch.1
P60/PPG10 P61/PPG11 P62/TO10
UART/SIO 8/16-bit compound timer ch.1
P63/TO11 P64/EC1 P65/SCK
P13/TRG0/ADTG P14/PPG0 P20/PPG00 P21/PPG01 P22/TO00 P23/TO01 P24/EC0 P30/AN00 to P37/AN07 P40/AN08 to P43/AN11 AVCC AVSS AVR P50/SCL0 P51/SDA0 P52/PPG1 P53/TRG1
LIN-UART
8/16-bit PPG ch.0
P66/SOT P67/SIN P70/TO0 P71/TI0 P80 to P83
8/16-bit compound timer ch.0
16-bit reload timer
External interrupt ch.8 to ch.11
PE0/INT10 to PE3/INT13
8/10-bit A/D converter
I 2C
16-bit PPG ch.1 Port Port
Other pins
MOD, VCC, VSS, C
* : Single clock product is general-purpose port, and dual clock product is sub clock oscillation pin.
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MB95100AM Series
CPU CORE
1. Memory space
Memory space of the MB95100AM series is 64 Kbytes and consists of I/O area, data area, and program area. The memory space includes special-purpose areas such as the general-purpose registers and vector table. Memory map of the MB95100AM series is shown below.
* Memory Map
MB95F104AMS/F104ANS/F104AJS MB95F106AMS/F106ANS/F106AJS MB95F108AMS/F108ANS/F108AJS MB95F104AMW/F104ANW/F104AJW MB95F106AMW/F106ANW/F106AJW MB95F108AMW/F108ANW/F108AJW 0000H I/O 0080H 0100H 0200H 0880H 0F80H 1000H RAM 2 Kbytes
Register
MB95108AM 0000H
MB95FV100D-103 I/O
I/O 0080H RAM 0100H Register 0200H Address #1 0F80H Address #2
0000H 0080H
RAM 3.75 Kbytes 0100H Register 0200H
Access prohibited Extension I/O
Access prohibited Extension I/O 0F80H 1000H Extension I/O
MASK ROM 60 Kbytes
Flash memory
Flash memory 60 Kbytes
FFFFH
FFFFH
FFFFH
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MB95100AM Series
Flash MB95F104AMS/F104ANS/F104AJS MB95F104AMW/F104ANW/F104AJW MB95F106AMS/F106ANS/F106AJS MB95F106AMW/F106ANW/F106AJW MB95F108AMS/F108ANS/F108AJS MB95F108AMW/F108ANW/F108AJW 16 Kbytes 32 Kbytes 60 Kbytes
RAM 512 bytes 1 Kbyte 2 Kbytes
Address #1 0280H 0480H 0880H
Address #2 C000H 8000H 1000H
22
MB95100AM Series
2. Register
The MB95100AM series has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The dedicated registers are as follows: Program counter (PC) : A 16-bit register to indicate locations where instructions are stored. Accumulator (A) : A 16-bit register for temporary storage of arithmetic operations. In the case of an 8-bit data processing instruction, the lower one byte is used. Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator. In the case of an 8-bit data processing instruction, the lower one byte is used. Index register (IX) : A 16-bit register for index modification. Extra pointer (EP) : A 16-bit pointer to point to a memory address. Stack pointer (SP) : A 16-bit register to indicate a stack area. Program status (PS) : A 16-bit register for storing a register bank pointer, a direct bank pointer, and a condition code register.
16-bit
PC A T IX EP SP PS
Initial Value : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status FFFDH 0000H 0000H 0000H 0000H 0000H 0030H
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer (DP) and the lower 8 bits for use as a condition code register (CCR) . (Refer to the diagram below.) * Structure of the Program Status
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 PS R4 R3 R2 R1 R0 DP2 DP1 bit 8 DP0 bit 7 H bit 6 I bit 5 IL1 bit 4 IL0 bit 3 N bit 2 Z bit 1 V bit 0 C
RP
DP
CCR
23
MB95100AM Series
The RP indicates the address of the register bank currently being used. The relationship between the content of RP and the real address conforms to the conversion rule illustrated below: * Rule for Conversion of Actual Addresses in the General-purpose Register Area RP upper
"0" "0" "0" "0" "0" "0" "0" A9 "1" A8 R4 A7 R3 A6 R2 A5 R1 A4 R0 A3
OP code lower
b2 A2 b1 A1 b0 A0
Generated address
A15 A14 A13 A12 A11 A10
The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using direct addresses to 0080H to 00FFH. Direct bank pointer (DP2 to DP0) Specified address area Mapping area XXXB (no effect to mapping) 000B (initial value) 001B 010B 011B 100B 101B 110B 111B 0080H to 00FFH 0000H to 007FH 0000H to 007FH (without mapping) 0080H to 00FFH (without mapping) 0100H to 017FH 0180H to 01FFH 0200H to 027FH 0280H to 02FFH 0300H to 037FH 0380H to 03FFH 0400H to 047FH
The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that control CPU operations at interrupt. H flag : Set to "1" when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared to "0" otherwise. This flag is for decimal adjustment instructions. I flag : Interrupt is enabled when this flag is set to "1". Interrupt is disabled when this flag is set to "0". The flag is set to "0" when reset. IL1, IL0 : Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 0 0 1 1 N flag Z flag V flag C flag IL0 0 1 0 1 Interrupt level 0 1 2 3 Low = no interruption Priority High
: Set to "1" if the MSB is set to "1" as the result of an arithmetic operation. Cleared to "0" when the
bit is set to "0".
: Set to "1" when an arithmetic operation results in "0". Cleared to "0" otherwise. : Set to "1" if the complement on 2 overflows as a result of an arithmetic operation. Cleared to "0"
otherwise. : Set to "1" when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to "0" otherwise. Set to the shift-out value in the case of a shift instruction.
24
MB95100AM Series
The following general-purpose registers are provided: General-purpose registers: 8-bit data storage registers The general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains 8registers. Up to a total of 32 banks can be used on the MB95100AM series. The bank currently in use is specified by the register bank pointer (RP), and the lower 3 bits of OP code indicates the general-purpose register 0 (R0) to general-purpose register 7 (R7). * Register Bank Configuration
8-bit 1F8H This address = 0100H + 8 x (RP) Address 100H R0 R1 R2 R3 R4 R5 107H R6 R7 Bank 0 R0 R0 R1 R2 R3 R4 R5 R6 R7 R1 R2 R3 R4 R5 R6 1FFH R7 Bank 31
32 banks 32 banks (RAM area) The number of banks is limited by the usable RAM capacitance.
Memory area
25
MB95100AM Series
I/O MAP
Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH 0010H 0011H 0012H 0013H 0014H 0015H 0016H 0017H 0018H 0019H 001AH 001BH 001CH to 0025H 0026H 0027H 0028H, 0029H 002AH Register abbreviation PDR0 DDR0 PDR1 DDR1 WATR PLLC SYCC STBC RSRR TBTC WPCR WDTC PDR2 DDR2 PDR3 DDR3 PDR4 DDR4 PDR5 DDR5 PDR6 DDR6 PDR7 DDR7 PDR8 DDR8 PDRE DDRE PDRG Register name Port 0 data register Port 0 direction register Port 1 data register Port 1 direction register (Disabled) Oscillation stabilization wait time setting register PLL control register System clock control register Standby control register Reset source register Timebase timer control register Watch prescaler control register Watchdog timer control register (Disabled) Port 2 data register Port 2 direction register Port 3 data register Port 3 direction register Port 4 data register Port 4 direction register Port 5 data register Port 5 direction register Port 6 data register Port 6 direction register Port 7 data register Port 7 direction register Port 8 data register Port 8 direction register (Disabled) Port E data register Port E direction register (Disabled) Port G data register R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B 00000000B 00000000B 00000000B 11111111B 00000000B 1010X011B 00000000B XXXXXXXXB 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B (Continued) 26
MB95100AM Series
Address 002BH 002CH 002DH 002EH 002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH 003FH 0040H, 0041H 0042H 0043H 0044H 0045H 0046H, 0047H 0048H 0049H 004AH 004BH 004CH 004DH
Register abbreviation DDRG PUL1 PUL2 PUL3 PUL4 PUL5 PUL7 PULE PULG T01CR1 T00CR1 T11CR1 T10CR1 PC01 PC00 PC11 PC10 TMCSRH0 TMCSRL0 PCNTH0 PCNTL0 PCNTH1 PCNTL1 EIC00 EIC10 EIC20 EIC30 EIC01 EIC11
Register name Port G direction register (Disabled) Port 1 pull-up register Port 2 pull-up register Port 3 pull-up register Port 4 pull-up register Port 5 pull-up register Port 7 pull-up register (Disabled) Port E pull-up register Port G pull-up register 8/16-bit compound timer 01 control status register 1 ch.0 8/16-bit compound timer 00 control status register 1 ch.0 8/16-bit compound timer 11 control status register 1 ch.1 8/16-bit compound timer 10 control status register 1 ch.1 8/16-bit PPG1 control register ch.0 8/16-bit PPG0 control register ch.0 8/16-bit PPG1 control register ch.1 8/16-bit PPG0 control register ch.1 16-bit reload timer control status register (Upper byte) ch.0 16-bit reload timer control status register (Lower byte) ch.0 (Disabled) 16-bit PPG status control register (Upper byte) ch.0 16-bit PPG status control register (Lower byte) ch.0 16-bit PPG status control register (Upper byte) ch.1 16-bit PPG status control register (Lower byte) ch.1 (Disabled) External interrupt circuit control register ch.0/ch.1 External interrupt circuit control register ch.2/ch.3 External interrupt circuit control register ch.4/ch.5 External interrupt circuit control register ch.6/ch.7 External interrupt circuit control register ch.8/ch.9 External interrupt circuit control register ch.10/ch.11
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B (Continued) 27
MB95100AM Series
Address 004EH, 004FH 0050H 0051H 0052H 0053H 0054H 0055H 0056H 0057H 0058H 0059H 005AH 005BH to 005FH 0060H 0061H 0062H 0063H 0064H 0065H 0066H to 006BH 006CH 006DH 006EH 006FH 0070H 0071H 0072H 0073H 0074H 0075H 0076H 0077H
Register abbreviation SCR SMR SSR RDR/TDR ESCR ECCR SMC10 SMC20 SSR0 TDR0 RDR0 IBCR00 IBCR10 IBSR0 IDDR0 IAAR0 ICCR0 ADC1 ADC2 ADDH ADDL WCSR FSR SWRE0 SWRE1 WREN WROR
2
Register name (Disabled) LIN-UART serial control register LIN-UART serial mode register LIN-UART serial status register LIN-UART reception/transmission data register LIN-UART extended status control register LIN-UART extended communication control register UART/SIO serial mode control register 1 ch.0 UART/SIO serial mode control register 2 ch.0 UART/SIO serial status register ch.0 UART/SIO serial output data register ch.0 UART/SIO serial input data register ch.0 (Disabled) I2C bus control register 0 ch.0 I2C bus control register 1 ch.0 I2C bus status register ch.0 I C data register ch.0 I C address register ch.0 I2C clock control register ch.0 (Disabled) 8/10-bit A/D converter control register 1 8/10-bit A/D converter control register 2 8/10-bit A/D converter data register (Upper byte) 8/10-bit A/D converter data register (Lower byte) Watch counter status register (Disabled) Flash memory status register Flash memory sector writing control register 0 Flash memory sector writing control register 1 (Disabled) Wild register address compare enable register Wild register data test setting register
2
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 00000000B 00000000B 00001000B 00000000B 00000100B 000000XXB 00000000B 00100000B 00000001B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 000X0000B 00000000B 00000000B 00000000B 00000000B (Continued)
28
MB95100AM Series
Address 0078H 0079H 007AH 007BH 007CH 007DH 007EH 007FH 0F80H 0F81H 0F82H 0F83H 0F84H 0F85H 0F86H 0F87H 0F88H 0F89H to 0F91H 0F92H 0F93H 0F94H 0F95H 0F96H 0F97H 0F98H 0F99H 0F9AH 0F9BH 0F9CH 0F9DH 0F9EH 0F9FH
Register abbreviation ILR0 ILR1 ILR2 ILR3 ILR4 ILR5 WRARH0 WRARL0 WRDR0 WRARH1 WRARL1 WRDR1 WRARH2 WRARL2 WRDR2 T01CR0 T00CR0 T01DR T00DR TMCR0 T11CR0 T10CR0 T11DR T10DR TMCR1 PPS01 PPS00 PDS01 PDS00
Register name Mirror of register bank pointer (RP) and direct bank pointer (DP) Interrupt level setting register 0 Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Interrupt level setting register 4 Interrupt level setting register 5 (Disabled) Wild register address setting register (Upper byte) ch.0 Wild register address setting register (Lower byte) ch.0 Wild register data setting register ch.0 Wild register address setting register (Upper byte) ch.1 Wild register address setting register (Lower byte) ch.1 Wild register data setting register ch.1 Wild register address setting register (Upper byte) ch.2 Wild register address setting register (Lower byte) ch.2 Wild register data setting register ch.2 (Disabled) 8/16-bit compound timer 01 control status register 0 ch.0 8/16-bit compound timer 00 control status register 0 ch.0 8/16-bit compound timer 01 data register ch.0 8/16-bit compound timer 00 data register ch.0 8/16-bit compound timer 00/01 timer mode control register ch.0 8/16-bit compound timer 11 control status register 0 ch.1 8/16-bit compound timer 10 control status register 0 ch.1 8/16-bit compound timer 11 data register ch.1 8/16-bit compound timer 10 data register ch.1 8/16-bit compound timer 10/11 timer mode control register ch.1 8/16-bit PPG1 cycle setting buffer register ch.0 8/16-bit PPG0 cycle setting buffer register ch.0 8/16-bit PPG1 duty setting buffer register ch.0 8/16-bit PPG0 duty setting buffer register ch.0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 11111111B 11111111B 11111111B 11111111B (Continued) 29
MB95100AM Series
Address 0FA0H 0FA1H 0FA2H 0FA3H 0FA4H 0FA5H 0FA6H 0FA7H 0FA8H, 0FA9H 0FAAH 0FABH 0FACH 0FADH 0FAEH 0FAFH 0FB0H 0FB1H 0FB2H 0FB3H 0FB4H 0FB5H 0FB6H to 0FBBH 0FBCH 0FBDH 0FBEH 0FBFH 0FC0H, 0FC1H 0FC2H 0FC3H
Register abbreviation PPS11 PPS10 PDS11 PDS10 PPGS REVC TMRH0/ TMRLRH0 TMRL0/ TMRLRL0 PDCRH0 PDCRL0 PCSRH0 PCSRL0 PDUTH0 PDUTL0 PDCRH1 PDCRL1 PCSRH1 PCSRL1 PDUTH1 PDUTL1 BGR1 BGR0 PSSR0 BRSR0 AIDRH AIDRL
Register name 8/16-bit PPG1 cycle setting buffer register ch.1 8/16-bit PPG0 cycle setting buffer register ch.1 8/16-bit PPG1 duty setting buffer register ch.1 8/16-bit PPG0 duty setting buffer register ch.1 8/16-bit PPG start register 8/16-bit PPG output inversion register 16-bit timer register (Upper byte) ch.0/ 16-bit reload register (Upper byte) ch.0 16-bit timer register (Lower byte) ch.0/ 16-bit reload register (Lower byte) ch.0 (Disabled) 16-bit PPG down counter register (Upper byte) ch.0 16-bit PPG down counter register (Lower byte) ch.0 16-bit PPG cycle setting buffer register (Upper byte) ch.0 16-bit PPG cycle setting buffer register (Lower byte) ch.0 16-bit PPG duty setting buffer register (Upper byte) ch.0 16-bit PPG duty setting buffer register (Lower byte) ch.0 16-bit PPG down counter register (Upper byte) ch.1 16-bit PPG down counter register (Lower byte) ch.1 16-bit PPG cycle setting buffer register (Upper byte) ch.1 16-bit PPG cycle setting buffer register (Lower byte) ch.1 16-bit PPG duty setting buffer register (Upper byte) ch.1 16-bit PPG duty setting buffer register (Lower byte) ch.1 (Disabled) LIN-UART baud rate generator register 1 LIN-UART baud rate generator register 0 UART/SIO dedicated baud rate generator prescaler selection register ch.0 UART/SIO dedicated baud rate generator baud rate setting register ch.0 (Disabled) A/D input disable register (Upper byte) A/D input disable register (Lower byte)
R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 11111111B 11111111B 11111111B 11111111B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 11111111B 11111111B 11111111B 11111111B 00000000B 00000000B 11111111B 11111111B 11111111B 11111111B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B (Continued)
30
MB95100AM Series
(Continued) Address 0FC4H to 0FE2H 0FE3H 0FE4H to 0FE6H 0FE7H 0FE8H, 0FE9H 0FEAH 0FEBH to 0FEDH 0FEEH 0FEFH 0FF0H to 0FFFH Register abbreviation WCDR ILSR2 CSVCR ILSR WICR Register name (Disabled) Watch counter data register (Disabled) Input level select register 2 (Disabled) Clock supervisor control register (Disabled) Input level select register Interrupt pin control register (Disabled) R/W R/W R/W R/W R/W R/W Initial value 00111111B 00000000B 00011100B 00000000B 01000000B
* R/W access symbols R/W : Readable/Writable R : Read only W : Write only * Initial value symbols 0 : The initial value of this bit is "0". 1 : The initial value of this bit is "1". X : The initial value of this bit is undefined. Note : Do not write to the " (Disabled) ". Reading the " (Disabled) " returns an undefined value.
31
MB95100AM Series
INTERRUPT SOURCE TABLE
Interrupt source External interrupt ch.0 External interrupt ch.4 External interrupt ch.1 External interrupt ch.5 External interrupt ch.2 External interrupt ch.6 External interrupt ch.3 External interrupt ch.7 UART/SIO ch.0 8/16-bit compound timer ch.0 (Lower) 8/16-bit compound timer ch.0 (Upper) LIN-UART (reception) LIN-UART (transmission) 8/16-bit PPG ch.1 (Lower) 8/16-bit PPG ch.1 (Upper) 16-bit reload timer ch.0 8/16-bit PPG ch.0 (Upper) 8/16-bit PPG ch.0 (Lower) 8/16-bit compound timer ch.1 (Upper) 16-bit PPG ch.0 I2C ch.0 16-bit PPG ch.1 8/10-bit A/D converter Timebase timer Watch prescaler/Watch counter External interrupt ch.8 External interrupt ch.9 External interrupt ch.10 External interrupt ch.11 8/16-bit compound timer ch.1 (Lower) Flash memory IRQ22 IRQ23 FFCEH FFCCH FFCFH FFCDH L22 [1 : 0] L23 [1 : 0] Low IRQ21 FFD0H FFD1H L21 [1 : 0] Interrupt request number IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IRQ16 IRQ17 IRQ18 IRQ19 IRQ20 Vector table address Upper FFFAH FFF8H FFF6H FFF4H FFF2H FFF0H FFEEH FFECH FFEAH FFE8H FFE6H FFE4H FFE2H FFE0H FFDEH FFDCH FFDAH FFD8H FFD6H FFD4H FFD2H Lower FFFBH FFF9H FFF7H FFF5H FFF3H FFF1H FFEFH FFEDH FFEBH FFE9H FFE7H FFE5H FFE3H FFE1H FFDFH FFDDH FFDBH FFD9H FFD7H FFD5H FFD3H Same level Bit name of priority order interrupt level (at simultaneous setting register occurrence) L00 [1 : 0] L01 [1 : 0] L02 [1 : 0] L03 [1 : 0] L04 [1 : 0] L05 [1 : 0] L06 [1 : 0] L07 [1 : 0] L08 [1 : 0] L09 [1 : 0] L10 [1 : 0] L11 [1 : 0] L12 [1 : 0] L13 [1 : 0] L14 [1 : 0] L15 [1 : 0] L16 [1 : 0] L17 [1 : 0] L18 [1 : 0] L19 [1 : 0] L20 [1 : 0] High
32
MB95100AM Series
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Symbol Vcc AVcc AVR Input voltage*
1 1
Rating Min Vss - 0.3 Vss - 0.3 Vss - 0.3 Vss - 0.3 - 2.0 Max Vss + 6.0 Vss + 6.0 Vss + 6.0 Vss + 6.0 + 2.0 20 15 15
Unit *2 *2 *3 V mA mA mA *3
Remarks
Power supply voltage*
1
V
VI VO ICLAMP |ICLAMP| IOL1 IOL2
Output voltage*
Maximum clamp current Total maximum clamp current "L" level maximum output current
Applicable to pins*4 Applicable to pins*4 Other than P00 to P07 P00 to P07 Other than P00 to P07 Average output current = operating current x operating ratio (1 pin) P00 to P07 Average output current = operating current x operating ratio (1 pin)
IOLAV1 "L" level average current IOLAV2
4 mA 12
"L" level total maximum output current "L" level total average output current "H" level maximum output current
IOL IOLAV IOH1 IOH2

100
mA Total average output current = operating current x operating ratio (Total of pins) Other than P00 to P07 P00 to P07 Other than P00 to P07 Average output current = operating current x operating ratio (1 pin) P00 to P07 Average output current = operating current x operating ratio (1 pin)
50 - 15 - 15 -4
mA
mA
IOHAV1 "H" level average current IOHAV2
mA -8
"H" level total maximum output current "H" level total average output current
IOH IOHAV

- 100 - 50
mA Total average output current = operating current x operating ratio (Total of pins) (Continued)
mA
33
MB95100AM Series
(Continued) Parameter Power consumption Operating temperature Storage temperature Symbol Pd TA Tstg Rating Min - 40 - 55 Max 320 + 85 + 150 Unit mW C C
*1 : The parameter is based on AVSS = VSS = 0.0 V. *2 : Apply equal potential to AVcc and Vcc. AVR should not exceed AVcc + 0.3 V. *3 : VI and Vo should not exceed VCC + 0.3 V. VI must not exceed the rating voltage. However, if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *4 : Applicable to pins : P00 to P07, P10 to P14, P20 to P24, P30 to P37, P40 to P43, P52, P53, P70, P71, PE0 to PE3 * Use within recommended operating conditions. * Use at DC voltage (current). * +B signal is an input signal that exceeds VCC voltage. The + B signal should always be applied a limiting resistance placed between the + B signal and the microcontroller. * The value of the limiting resistance should be set so that when the + B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. * Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this affect other devices. * Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result. * Note that if the + B input is applied during power-on, the power supply is provided from the pins and the resulting power supply voltage may not be sufficient to operate the power-on reset. * Care must be taken not to leave the + B input pin open. * Sample recommended circuits : * Input/Output Equivalent circuits Protective diode Limiting resistance
Vcc P-ch N-ch R
+ B input (0 V to 16 V)
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
34
MB95100AM Series
2. Recommended Operating Conditions
(AVss = Vss = 0.0 V) Parameter Symbol Pin name Conditions Value Min 2.42*1 Max 5.5 Unit At normal operating Retain status of stop operation At normal operating Retain status of stop operation V F C MB95FV100D-103 Other than MB95FV100D-103 Remarks
2.3 Power supply voltage VCC, AVCC 2.7
5.5 V 5.5
2.3
5.5
A/D converter reference input voltage Smoothing capacitor Operating temperature
AVR

4.0
AVCC
CS TA
0.1 - 40 +5
1.0 + 85 + 35
*2 Other than MB95FV100D-103 MB95FV100D-103
*1 : The value is 2.88 V when the low voltage detection reset is used. *2 : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of VCC pin must have a capacitance value higher than CS. For connection of smoothing capacitor CS, refer to the diagram below. * C pin connection diagram
C
CS
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
35
MB95100AM Series
3. DC Characteristics
(Vcc = AVcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter
Symbol
Pin name
Conditions
Value Min 0.7 Vcc Typ Max Vcc + 0.3
Unit
Remarks Hysteresis input of CMOS input level Pin input at selecting of Automotive input level
VIH P10, P50, P51, P67 P00 to P07, P10 to P14, P20 to P24, P30 to P37, P40 to P43, P50 to P53, VIHA P60 to P67, P70, P71, P80 to P83, PE0 to PE3, PG1*2, PG2*2 "H" level input voltage P00 to P07, P10 to P14, P20 to P24, P30 to P37, P40 to P43, P50 to P53, VIHS P60 to P67, P70, P71, P80 to P83, PE0 to PE3, PG1*2, PG2*2
*1
V
0.8 VCC
VCC + 0.3
V
*1
0.8 Vcc
Vcc + 0.3
V
Hysteresis input
VIHM RST, MOD
0.7 Vcc
Vcc + 0.3
V
CMOS input (MASK ROM product is hysteresis input) Hysteresis input of CMOS input level Pin input at selecting of Automotive input level
VIL
P10, P50, P51, P67
*1
Vss - 0.3
0.3 Vcc
V
P00 to P07, P10 to P14, P20 to P24, P30 to P37, P40 to P43, P50 to P53, VILA P60 to P67, P70, P71, P80 to P83, PE0 to PE3, PG1*2, PG2*2 "L" level input voltage P00 to P07, P10 to P14, P20 to P24, P30 to P37, P40 to P43, P50 to P53, VILS P60 to P67, P70, P71, P80 to P83, PE0 to PE3, PG1*2, PG2*2
VSS - 0.3
0.5 VCC
V
*1
Vss - 0.3
0.2 Vcc
V
Hysteresis input
VILM RST, MOD
Vss - 0.3
0.3 Vcc
V
CMOS input (MASK ROM product is hysteresis input) (Continued)
36
MB95100AM Series
(Vcc = AVcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter Open-drain output application voltage "H" level output voltage
Symbol
Pin name
Conditions
Value Min Vss - 0.3 VCC - 0.5 VCC - 0.5 -5 Typ Max Vss + 5.5 0.4 0.4 +5
Unit
Remarks
VD
P50, P51, P80 to P83 Output pin other than P00 to P07
IOH = - 4.0 mA IOH = - 8.0 mA IOL = 4.0 mA IOL = 12 mA 0.0 V < VI < Vcc
V
VOH1

V V V V A When the pull-up prohibition setting
VOH2 P00 to P07
Output pin other than "L" level output VOL1 P00 to P07, RST*3 voltage VOL2 P00 to P07 Input leakage current (Hi-Z output leakage current) Open-drain output leakage current Port other than P50, P51, P80 to P83
ILI
ILIOD
P50, P51, P80 to P83
0.0 V < VI < Vss + 5.5 V
5
A
P10 to P14,P20 to P24, P30 to P37, P40 to P43, Pull-up resistor RPULL P52, P53, P70, P71, VI = 0.0 V PE0 to PE3, PG1*2, PG2*2 Pull-down resistor Input capacitance RMOD MOD CIN VI = Vcc
25
50
100
k
When the pull-up permission setting
25
50 5
100 15
k MASK ROM product pF Flash memory product mA (At other than writing and erasing) Flash memory product mA (At writing and erasing) mA MASK ROM product Flash memory product mA (At other than writing and erasing) Flash memory product mA (At writing and erasing) mA MASK ROM product (Continued)
Other than AVcc, AVss, f = 1 MHz AVR, Vcc, Vss VCC = 5.5 V FCH = 20 MHz FMP = 10 MHz Main clock mode (divided by 2)
9.5
12.5

30 7.2 15.2
35 9.5 20.0
Power supply current*4
ICC
Vcc (External clock operation)
FCH = 32 MHz FMP = 16 MHz Main clock mode (divided by 2)

35.7 11.6
42.5 15.2
37
MB95100AM Series
(Vcc = AVcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C ) Parameter Symbol Pin name Conditions VCC = 5.5 V FCH = 20 MHz FMP = 10 MHz Main sleep mode (divided by 2) FCH = 32 MHz FMP = 16 MHz Main sleep mode (divided by 2) VCC = 5.5 V FCL = 32 kHz FMPL = 16 kHz Sub clock mode (divided by 2) , TA = + 25 C VCC = 5.5 V FCL = 32 kHz FMPL = 16 kHz Sub sleep mode (divided by 2) , TA = + 25 C VCC = 5.5 V FCL = 32 kHz Watch mode Main stop mode TA = + 25 C VCC = 5.5 V FCH = 4 MHz FMP = 10 MHz Main PLL mode (multiplied by 2.5) FCH = 6.4 MHz FMP = 16 MHz Main PLL mode (multiplied by 2.5) VCC = 5.5 V FCL = 32 kHz FMPL = 128 kHz Sub PLL mode (multiplied by 4) , TA = + 25 C Value Min Typ Max Unit Remarks
4.5
7.5
mA
ICCS
7.2
12.0
mA
ICCL
45
100
A
Dual clock product only
ICCLS Power supply current*4 ICCT Vcc (External clock operation)
10
81
A
Dual clock product only
4.6
27.0
A
Dual clock product only

9.3 7.0 14.9 11.2
12.5 9.5 20.0 15.2
mA mA mA mA
Flash memory product MASK ROM product Flash memory product MASK ROM product
ICCMPLL
ICCSPLL
160
400
A
Dual clock product only
(Continued)
38
MB95100AM Series
(Continued) Symbol (Vcc = AVcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Pin name Conditions VCC = 5.5 V FCH = 10 MHz Timebase timer mode TA = + 25 C VCC = 5.5 V Sub stop mode TA = + 25 C Current consumption for low voltage detection circuit only At oscillating 100 kHz current consumption of internal CR oscillator VCC = 5.5 V FCH = 16 MHz At operating of A/D conversion AVcc IAH VCC = 5.5 V FCH = 16 MHz At stopping A/D conversion TA = + 25 C Value Min Typ Max Unit Remarks
Parameter
ICTS
VCC (External clock operation)
0.15
1.10
mA
ICCH
3.5
20
A
Main stop mode for single clock product
ILVD Power supply current*4 VCC ICSV
38
50
A
20
36
A
IA
2.4
4.7
mA
1
5
A
*1 : P10, P50, P51, and P67 can switch the input level to either the "CMOS input level" or "hysteresis input level". The switching of the input level can be set by the input level selection register (ILSR). *2 : Single clock products only *3 : Product without clock supervisor only *4 : * The power-supply current is determined by the external clock. When the low voltage detection option is selected, the power-supply current will be a value of adding current consumption of the low voltage detection circuit (ILVD) to the specified value. Also, when both low voltage detection option and clock supervisor are selected, the power-supply current will be a value of adding current consumption of the low voltage detection circuit (ILVD) and current consumption of internal CR oscillator (ICSV) to the specified value. * Refer to "4. AC Characteristics (1) Clock Timing" for FCH and FCL. * Refer to "4. AC Characteristics (2) Source Clock/Machine Clock" for FMP and FMPL.
39
MB95100AM Series
4. AC Characteristics
(1) Clock Timing (Vcc = 2.42 V to 5.0 V, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter SymCondiPin name bol tions Value Min 1.00 1.00 FCH Clock frequency X0, X1 3.00 3.00 3.00 FCL X0A, X1A Clock cycle time tHCYL tLCYL tWH1 tWL1 tWH2 tWL2 tCR tCF X0, X1 X0A, X1A X0 X0A X0, X0A 61.5 30.8 61.5 Typ 32.768 32.768 30.5 15.2 Max 16.25 32.50 10.00 8.13 6.50 1000 1000 5 Unit MHz Remarks When using main oscillation circuit
MHz When using external clock MHz Main PLL multiplied by 1 MHz Main PLL multiplied by 2 MHz Main PLL multiplied by 2.5 kHz kHz ns ns s ns s ns When using sub oscillation circuit When using sub PLL When using oscillation circuit When using external clock When using sub clock When using external clock Duty ratio is about 30% to 70%. When using external clock
Input clock pulse width
Input clock rise time and fall time
40
MB95100AM Series
tHCYL tWH1 tCR tCF 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 0.2 VCC tWL1
X0
* Figure of main clock input port external connection When using a crystal or ceramic oscillator
Microcontroller
X0 X1 FCH
When using external clock
Microcontroller
X0 X1
Open
FCH
tLCYL tWH2 tCR tCF 0.8 VCC 0.8 VCC 0.1 VCC 0.1 VCC 0.1 VCC tWL2
X0A
* Figure of sub clock input port external connection When using a crystal or ceramic oscillator
Microcontroller
X0A X1A FCL
When using external clock
Microcontroller
X0A X1A
Open
FCL
41
MB95100AM Series
(2) Source Clock/Machine Clock (Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter Sym- Pin bol name Value Min 61.5 tSCLK 7.6 FSP FSPL 0.50 16.384 61.5 tMCLK 7.6 FMP FMPL 0.031 1.024 976.5 16.250 s 61.0 16.25 s Typ Max 2000 Unit Remarks When using main clock Min : FCH = 16.25 MHz, PLL multiplied by 1 Max : FCH = 1 MHz, divided by 2 When using sub clock Min : FCL = 32 kHz, PLL multiplied by 4 Max : FCL = 32 kHz, divided by 2
Source clock*1 (Clock before setting division)
ns
Source clock frequency
MHz When using main clock When using main clock Min : FSP = 16.25 MHz, no division Max : FSP = 0.5 MHz, divided by 16 When using sub clock Min : FSPL = 131 kHz, no division Max : FSPL = 16 kHz, divided by 16
131.072 kHz When using sub clock 32000 ns
Machine clock*2 (Minimum instruction execution time)
Machine clock frequency
MHz When using main clock
131.072 kHz When using sub clock
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it becomes the machine clock. Further, the source clock can be selected as follows. * Main clock divided by 2 * PLL multiplication of main clock (select from 1, 2, 2.5 multiplication) * Sub clock divided by 2 * PLL multiplication of sub clock (select from 2, 3, 4 multiplication) *2 : Operation clock of the microcontroller. Machine clock can be selected as follows. * Source clock (no division) * Source clock divided by 4 * Source clock divided by 8 * Source clock divided by 16
42
MB95100AM Series
* Outline of clock generation block
FCH (main oscillation) Divided by 2
Main PLL x1 x2 x 2.5 SCLK ( source clock ) FCL (sub oscillation) Divided by 2 Clock mode select bit ( SYCC : SCS1, SCS0 )
Division circuit x1 x 1/4 x 1/8 x 1/16
MCLK ( machine clock )
Sub PLL x2 x3 x4
43
MB95100AM Series
* Operating voltage - Operating frequency (TA = - 40 C to + 85 C)
* MB95F104AMS/F104ANS/F104AJS/F106AMS/F106ANS/F106AJS/F108AMS/F108ANS/F108AJS/F104AMW/ MB95F104ANW/F104AJW/F106AMW/F106ANW/F106AJW/F108AMW/F108ANW/F108AJW Sub PLL, Sub clock mode, watch mode, operating guarantee range Main clock mode, main PLL mode operating guarantee range
5.5
Operating voltage (V)
Operating voltage (V)
5.5
3.5 2.42
2.42
16.384 kHz
32 kHz
131.072 kHz
0.5 MHz 3 MHz
10 MHz
16.25 MHz
PLL operating guarantee range Source clock frequency (FSPL)
* MB95FV100D-103 Sub PLL, sub clock mode and watch mode operation guarantee range
5.5
PLL operating guarantee range Main clock operating guarantee range
Source clock frequency (FSP)
* Operating voltage - Operating frequency (TA = + 5 C to + 35 C)
Main clock mode and main PLL mode operation guarantee range
5.5
Operating voltage (V)
Operating voltage (V)
3.5 2.7
2.7
16.384 kHz
32 kHz
131.072 kHz
0.5 MHz 3 MHz
10 MHz
16.25 MHz
PLL operation guarantee range
PLL operation guarantee range Main clock operation guarantee range
Source clock frequency (FSPL)
Source clock frequency (FSP)
44
MB95100AM Series
* Main PLL operation frequency
16 MHz 15 MHz 14 MHz 13 MHz
Source clock frequency (FSP)
12 MHz 11 MHz 10 MHz 9 MHz 8 MHz 7.5MHz 7 MHz 6 MHz 5 MHz 4 MHz 3 MHz 0 MHz 3 MHz 4 MHz 5 MHz 6.4 MHz 8 MHz 10 MHz
x 2.5 x2 x1
Main clock frequency (FMP)
45
MB95100AM Series
(3) External Reset (Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter Symbol Value Min 2 tMCLK*1 RST "L" level pulse width tRSTL Oscillation time of oscillator* + 100 100 *1 : Refer to " (2) Source Clock/Machine Clock" for tMCLK. *2 : Oscillation time of oscillator is the time that the amplitude reaches 90 %. In the crystal oscillator, the oscillation time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between hundreds of s and several ms. In the external clock, the oscillation time is 0 ms. * At normal operating
2
Max
Unit ns s s
Remarks At normal operating At stop mode, sub clock mode, sub sleep mode, and watch mode At timebase timer mode
tRSTL
RST
0.2 VCC 0.2 VCC
* At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on
tRSTL 0.2 VCC 0.2 VCC
RST
90% of amplitude
X0
Internal operating clock Oscillation time Oscillation stabilization wait time of oscillator Execute instruction Internal reset
100 s
46
MB95100AM Series
(4) Power-on Reset (AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter Power supply rising time Power supply cutoff time Symbol tR tOFF Conditions Value Min 1 Max 50 Unit ms ms Waiting time until power-on Remarks
tR 2.5 V
tOFF
VCC
0.2 V
0.2 V
0.2 V
Note : Sudden change of power supply voltage may activate the power-on reset function. When changing power supply voltages during operation, set the slope of rising within 30 mV/ms as shown below .
VCC
2.3 V
Limiting the slope of rising within 30 mV/ms is recommended. Hold condition in STOP mode
VSS
47
MB95100AM Series
(5) Peripheral Input Timing (Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter Peripheral input "H" pulse width Peripheral input "L" pulse width Symbol tILIH tIHIL Pin name INT00 to INT07, INT10 to INT13, EC0, EC1, TI0, TRG0/ADTG, TRG1 Value Min 2 tMCLK* 2 tMCLK* Max Unit ns ns
* : Refer to " (2) Source Clock/Machine Clock" for tMCLK.
tILIH
tIHIL
INT00 to INT07, INT10 to INT13, EC0, EC1, TI0, TRG0/ADTG, TRG1
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
48
MB95100AM Series
(6) UART/SIO, Serial I/O Timing (Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter Serial clock cycle time UCK UO time Valid UI UCK UCK valid UI hold time Serial clock "H" pulse width Serial clock "L" pulse width UCK UO time Valid UI UCK UCK valid UI hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name UCK0 UCK0, UO0 UCK0, UI0 UCK0, UI0 UCK0 UCK0 UCK0, UO0 UCK0, UI0 UCK0, UI0 External clock operation Internal clock operation Conditions Value Min 4 tMCLK* - 190 2 tMCLK* 2 tMCLK* 4 tMCLK* 4 tMCLK* 2 tMCLK* 2 tMCLK* Max + 190 190 Unit ns ns ns ns ns ns ns ns ns
* : Refer to " (2) Source Clock/Machine Clock" for tMCLK.
* Internal shift clock mode
tSCYC
UCK0
0.8 V tSLOV
2.4 V 0.8 V
UO0
2.4 V 0.8 V tIVSH tSHIX 0.8 VCC 0.2 VCC
UI0
0.8 VCC 0.2 VCC
* External shift clock mode
tSLSH tSHSL 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tSLOV
UCK0
UO0
2.4 V 0.8 V tIVSH tSHIX 0.8 VCC 0.2 VCC
UI0
0.8 VCC 0.2 VCC
49
MB95100AM Series
(7) LIN-UART Timing Sampling at the rising edge of sampling clock*1 and prohibited serial clock delay*2 (ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0) (Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK valid SIN hold time Serial clock "L" pulse width Serial clock "H" pulse width SCK SOT delay time Valid SIN SCK SCK valid SIN hold time SCK fall time SCK rise time SymPin name bol tSCYC tSLOVI tIVSHI tSHIXI tSLSH tSHSL tIVSHE tSHIXE tF tR SCK Conditions Value Min 5 tMCLK*3 Max + 95 2 tMCLK*3 + 95 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns
Internal clock SCK, SOT - 95 operation output pin : SCK, SIN CL = 80 pF + 1 TTL. tMCLK*3 + 190 SCK, SIN 0 SCK SCK SCK, SIN SCK, SIN SCK SCK External clock operation output pin : CL = 80 pF + 1 TTL. 3 tMCLK* - tR
3
tMCLK* + 95
3
tSLOVE SCK, SOT
190 tMCLK* + 95
3

*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to " (2) Source Clock/Machine Clock" for tMCLK.
50
MB95100AM Series
* Internal shift clock mode
tSCYC 2.4 V 0.8 V tSLOVI 2.4 V 0.8 V tIVSHI tSHIXI 0.8 V
SCK
SOT
SIN
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
* External shift clock mode
tSLSH tSHSL 0.8 VCC 0.2 VCC tF tSLOVE 2.4 V 0.8 V tIVSHE tSHIXE 0.2 VCC tR 0.8 VCC
SCK
0.8 VCC
SOT
SIN
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
51
MB95100AM Series
Sampling at the falling edge of sampling clock*1 and prohibited serial clock delay*2 (ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0) (Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK SCK valid SIN hold time SCK fall time SCK rise time Symbol tSCYC tSHOVI tIVSLI tSLIXI tSHSL tSLSH tSHOVE tIVSLE tSLIXE tF tR Pin name SCK Internal clock SCK, SOT operation output pin : SCK, SIN CL = 80 pF + 1 TTL. SCK, SIN SCK SCK SCK, SOT SCK, SIN SCK, SIN SCK SCK External clock operation output pin : CL = 80 pF + 1 TTL. Conditions Value Min 5 tMCLK*3 - 95 tMCLK* + 190
3
Max + 95 2 tMCLK* + 95
3
Unit ns ns ns ns ns ns ns ns ns ns ns
0 3 tMCLK*3 - tR tMCLK* + 95
3
190 tMCLK*3 + 95
10 10
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to " (2) Source Clock/Machine Clock" for tMCLK.
52
MB95100AM Series
* Internal shift clock mode
tSCYC
SCK
2.4 V 0.8 V tSHOVI 2.4 V 0.8 V tIVSLI tSLIXI
2.4 V
SOT
SIN
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
* External shift clock mode
tSHSL tSLSH 0.8 VCC 0.2 VCC tSHOVE 2.4 V 0.8 V tIVSLE tSLIXE tF 0.2 VCC
SCK
0.2 VCC tR
0.8 VCC
SOT
SIN
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
53
MB95100AM Series
Sampling at the rising edge of sampling clock*1 and enabled serial clock delay*2 (ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1) (Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK valid SIN hold time SOT SCK delay time Symbol tSCYC tSHOVI tIVSLI tSLIXI tSOVLI Pin name SCK SCK, SOT SCK, SIN SCK, SIN SCK, SOT Internal clock operation output pin : CL = 80 pF + 1 TTL. Conditions Value Min 5 tMCLK*3 - 95 tMCLK* + 190
3
Max + 95 4 tMCLK*3
Unit ns ns ns ns ns
0
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to " (2) Source Clock/Machine Clock" for tMCLK.
tSCYC
SCK
0.8 V tSOVLI 2.4 V 0.8 V tIVSLI
2.4 V
tSHOVI
2.4 V 0.8 V tSLIXI 0.8 VCC 0.2 VCC
0.8 V
SOT
SIN
0.8 VCC 0.2 VCC
54
MB95100AM Series
Sampling at the falling edge of sampling clock*1 and enabled serial clock delay*2 (ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1) (Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK valid SIN hold time SOT SCK delay time Symbol tSCYC tSLOVI tIVSHI tSHIXI tSOVHI Pin name SCK SCK, SOT Internal clock SCK, SIN operating output pin : CL = 80 pF + 1 TTL. SCK, SIN Conditions Value Min 5 tMCLK*3 - 95 tMCLK* + 190
3
Max + 95 4 tMCLK*3
Unit ns ns ns ns ns
0
SCK, SOT
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to " (2) Source Clock/Machine Clock" for tMCLK.
tSCYC
SCK
tSOVHI
2.4 V 0.8 V tSLOVI 2.4 V 0.8 V tIVSHI tSHIXI 0.8 VCC 0.2 VCC 2.4 V 0.8 V
2.4 V
SOT
SIN
0.8 VCC 0.2 VCC
55
MB95100AM Series
(8) I2C Timing (Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Value Parameter Symbol Pin name SCL0 SCL0 SDA0 SCL0 SCL0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 R = 1.7 k, C = 50 pF*1 Conditions Standardmode Min SCL clock frequency (Repeat) Start condition hold time SDA SCL SCL clock "L" width SCL clock "H" width (Repeat) Start condition setup time SCL SDA Data hold time SCL SDA Data setup time SDA SCL Stop condition setup time SCL SDA Bus free time between stop condition and start condition fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF 0 4.0 4.7 4.0 4.7 0 0.25 4 4.7 Max 100 3.45*2 Fast-mode Min 0 0.6 1.3 0.6 0.6 0 0.1 0.6 1.3 Max 400 0.9*3 kHz s s s s s s s s Unit
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines. *2 : The maximum tHD;DAT have only to be met if the device dose not stretch the "L" width (tLOW) of the SCL signal. *3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met.
tWAKEUP SDA0 tLOW SCL0 tHD;STA tSU;DAT tSU;STA tSU;STO tHD;DAT tHIGH tHD;STA tBUF
56
MB95100AM Series
(Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter
SCL clock "L" width SCL clock "H" width
Sym- Pin Condition bol name
tLOW tHIGH SCL0 SCL0
Value*2 Min
(2 + nm / 2) tMCLK - 20 (nm / 2) tMCLK - 20
Max
(nm / 2 ) tMCLK + 20
Unit
ns ns
Remarks
Master mode Master mode Master mode Maximum value is applied when m, n = 1, 8. Otherwise, the minimum value is applied. Master mode Master mode
Start condition hold time
tHD;STA
SCL0 SDA0
(-1 + nm / 2) tMCLK - 20
(-1 + nm) tMCLK + 20
ns
Stop condition setup time Start condition setup time Bus free time between stop condition and start condition Data hold time
tSU;STO tSU;STA
SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0
(1 + nm / 2) tMCLK - 20 (1 + nm / 2) tMCLK + 20 (1 + nm / 2) tMCLK - 20 (1 + nm / 2) tMCLK + 20
ns ns
tBUF
(2 nm + 4) tMCLK - 20
ns
tHD;DAT
3 tMCLK - 20
ns
Master mode Master mode When assuming that "L" of SCL is not extended, the minimum value is applied to first bit of continuous data. Otherwise, the maximum value is applied. Minimum value is applied to interrupt at 9th SCL. Maximum value is applied to interrupt at 8th SCL. At reception At reception Undetected when 1 tMCLK is used at reception Undetected when 1 tMCLK is used at reception Undetected when 1 tMCLK is used at reception At reception At slave transmission mode At slave transmission mode
Data setup time
tSU;DAT
SCL0 SDA0
(-2 + nm / 2) tMCLK - 20 (-1 + nm / 2) tMCLK + 20
ns
R = 1.7 k, C = 50 pF*1
Setup time between clearing interrupt and tSU;INT SCL0 SCL rising
(nm / 2) tMCLK - 20
(1 + nm / 2) tMCLK + 20
ns
SCL clock "L" width SCL clock "H" width Start condition detection Stop condition detection Restart detection condition Bus free time Data hold time Data setup time
tLOW tHIGH
SCL0 SCL0
4 tMCLK - 20 4 tMCLK - 20 2 tMCLK - 20 2 tMCLK - 20 2 tMCLK - 20 2 tMCLK - 20 2 tMCLK - 20 tLOW - 3 tMCLK - 20

ns ns ns ns ns ns ns ns
SCL0 tHD;STA SDA0 tSU;STO tSU;STA tBUF tHD;DAT tSU;DAT SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0
(Continued)
57
MB95100AM Series
(Continued) (Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Sym- Pin Condition bol name tHD;DAT tSU;DAT SCL0 SDA0 SCL0 R = 1.7 k, SDA0 C = 50 pF*1 SCL0 SDA0 Value*2 Min 0 tMCLK - 20 Oscillation stabilization wait time + 2 tMCLK - 20 Max Unit ns ns Remarks At reception At reception
Parameter Data hold time Data setup time SDASCL (at wake-up function)
tWAKEUP
ns
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines. *2 : * Refer to " (2) Source Clock/Machine Clock" for tMCLK. * m is CS4 bit and CS3 bit (bit 4 and bit 3) of clock control register (ICCR0) . * n is CS2 bit to CS0 bit (bit 2 to bit 0) of clock control register (ICCR0) . * Actual timing of I2C is determined by m and n values set by the machine clock (tMCLK) and CS4 to CS0 of ICCR0 register. * Standard-mode : m and n can be set at the range : 0.9 MHz < tMCLK (machine clock) < 10 MHz. Setting of m and n limits the machine clock that can be used below. (m, n) = (1, 8) : 0.9 MHz < tMCLK 1 MHz (m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 MHz < tMCLK 2 MHz (m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 MHz < tMCLK 4 MHz (m, n) = (1, 98) : 0.9 MHz < tMCLK 10 MHz * Fast-mode : m and n can be set at the range : 3.3 MHz < tMCLK (machine clock) < 10 MHz. Setting of m and n limits the machine clock that can be used below. (m, n) = (1, 8) : 3.3 MHz < tMCLK 4 MHz (m, n) = (1, 22) , (5, 4) : 3.3 MHz < tMCLK 8 MHz (m, n) = (6, 4) : 3.3 MHz < tMCLK 10 MHz
58
MB95100AM Series
(9) Low Voltage Detection (AVss = Vss = 0.0 V, TA = -40 C to + 85 C) Parameter Release voltage Detection voltage Hysteresis width Power-supply start voltage Power-supply end voltage Power-supply voltage change time (at power supply rise) Symbol VDL+ VDLVHYS Voff Von Value Min 2.52 2.42 70 4.9 0.3 tr 300 tf td1 td2 ILVD 300 38 400 30 50 s s s A Current consumption for low voltage detection circuit only 3000 s s Typ 2.70 2.60 100 Max 2.88 2.78 2.3 Unit V V mV V V s Slope of power supply that reset release signal generates Slope of power supply that reset release signal generates within rating (VDL+) Slope of power supply that reset detection signal generates Slope of power supply that reset detection signal generates within rating (VDL-) Remarks At power-supply rise At power-supply fall
Power-supply voltage change time (at power supply fall) Reset release delay time Reset detection delay time Current consumption
VCC Von
Voff
VCC
tf
tr
time
VDL+ VDL-
VHYS
Internal reset signal time
td2
td1
59
MB95100AM Series
(10) Clock Supervisor Clock (Vcc = AVcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = -40 C to + 85 C) Parameter Oscillation frequency Oscillation start time Current consumption Symbol fOUT twk ICSV Value Min 50 Typ 100 20 Max 200 10 36 Unit kHz s A Current consumption of built-in CR oscillator, at oscillation of 100 kHz Remarks
60
MB95100AM Series
5. A/D Converter
(1) A/D Converter Electrical Characteristics (AVcc = Vcc = 4.0 V to 5.5 V, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter Resolution Total error Linearity error Differential linear error Zero transition voltage Full-scale transition voltage Compare time VOT VFST Symbol Value Min - 3.0 - 2.5 - 1.9 AVss - 1.5 LSB AVR - 3.5 LSB 0.9 1.8 0.6 Sampling time 1.2 Analog input current Analog input voltage Reference voltage Reference voltage supply current IAIN VAIN IR IRH - 0.3 AVss AVss + 4.0 600 + 0.3 AVR AVcc 900 5 s A V V A A AVR pin AVR pin, During A/D operation AVR pin, At stop mode Typ AVss + 0.5 LSB AVR - 1.5 LSB Max 10 + 3.0 + 2.5 + 1.9 AVss + 2.5 LSB AVR + 0.5 LSB 16500 16500 Unit bit LSB LSB LSB V V s s s 4.5 V AVcc 5.5 V 4.0 V AVcc < 4.5 V 4.5 V AVcc 5.5 V, At external impedance < 5.4 k 4.0 V AVcc < 4.5 V, At external impedance < 2.4 k Remarks
61
MB95100AM Series
(2) Notes on Using A/D Converter * About the external impedance of analog input and its sampling time A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/ D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 F to the analog input pin. * Analog input equivalent circuit
R
Analog input
C
Comparator
During sampling : ON 4.5 V AVcc 5.5 V 4.0 V AVcc < 4.5 V Note : The values are reference values. R 2.0 k (Max) 8.2 k (Max) C 16 pF (Max) 16 pF (Max)
* The relationship between external impedance and minimum sampling time (External impedance = 0 k to 100 k)
100 90 80 70 60 50 40 30 20 10 0 0 2 4
(External impedance = 0 k to 20 k)
20 18 16 14 12 10 8 6 4 2 0 0
External impedance [k]
External impedance [k]
AVCC 4.5 V
AVCC 4.5 V AVCC 4.0 V
AVCC 4.0 V
6
8
10
12
14
1
2
3
4
Minimum sampling time [s]
Minimum sampling time [s]
* About errors As |AVR - AVSS| becomes smaller, values of relative errors grow larger.
62
MB95100AM Series
(3) Definition of A/D Converter Terms * Resolution The level of analog variation that can be distinguished by the A/D converter. When the number of bits is 10, analog voltage can be divided into 210 = 1024. * Linearity error (unit : LSB) The deviation between the value along a straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") of a device and the full-scale transition point ("11 1111 1111" "11 1111 1110") compared with the actual conversion values obtained. * Differential linear error (Unit : LSB) Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. * Total error (unit: LSB) Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error, linearity error, quantum error, and noise.
Ideal I/O characteristics
VFST
Total error
3FFH 3FEH
3FFH 3FEH 1.5 LSB
Actual conversion characteristic {1 LSB x (N - 1) + 0.5 LSB}
Digital output
Digital output
3FDH
3FDH
004H 003H 002H 001H 0.5 LSB AVSS AVR VOT 1 LSB
004H 003H 002H 001H AVSS AVR VNT Actual conversion characteristic Ideal characteristics
Analog input 1 LSB = AVR - AVss 1024 (V)
Analog input
Total error of = VNT - {1 LSB x (N - 1) + 0.5 LSB} [LSB] digital output N 1 LSB
N : A/D converter digital output value VNT : A voltage at which digital output transits from (N - 1) to N. (Continued)
63
MB95100AM Series
(Continued) Zero transition error
004H
Actual conversion characteristic
Full-scale transition error
Ideal characteristics
3FFH
Digital output
003H
Ideal characteristics Actual conversion characteristic
Digital output
Actual conversion characteristic
3FEH
VFST
002H
3FDH
(measurement value)
001H
VOT (measurement value)
Actual conversion characteristic
3FCH
AVSS
AVR
AVSS
AVR
Analog input
Analog input
Linearity error
3FFH 3FEH 3FDH
Actual conversion characteristic
Differential linear error
Ideal characteristics
N+1H
Actual conversion characteristic VFST
(measurement value)
{1 LSB x N + VOT}
Digital output
Digital output
V (N+1)T
NH
VNT 004H 003H 002H 001H AVSS
Actual conversion characteristic Ideal characteristics
N-1H
VNT
Actual conversion characteristic
N-2H
VOT (measurement value)
AVR
AVSS
Analog input Linearity error in = VNT - {1 LSB x N + VOT} 1 LSB digital output N
Analog input
AVR
Differential linear error = in digital output N
V (N + 1) T - VNT 1 LSB
-1
N : A/D converter digital output value VNT : A voltage at which digital output transits from (N - 1) to N. VOT (Ideal value) = AVSS + 0.5 LSB [V] VFST (Ideal value) = AVR - 1.5 LSB [V]
64
MB95100AM Series
6. Flash Memory Program/Erase Characteristics
Parameter Sector erase time (4 Kbytes sector) Sector erase time (16 Kbytes sector) Byte programming time Erase/program cycle Power supply voltage at erase/ program Flash memory data retention time Value Min 10000 4.5 20*3 Typ 0.2*1 0.5*1 32 Max 0.5*2 7.5*2 3,600 5.5 Unit s s s cycle V year Average TA = +85 C Remarks Excludes 00H programming prior erasure. Excludes 00H programming prior erasure. Excludes system-level overhead.
*1 : TA = + 25 C, VCC = 5.0 V, 10000 cycles *2 : TA = + 85 C, VCC = 4.5 V, 10000 cycles *3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at +85 C) .
65
MB95100AM Series
MASK OPTION
MB95F104AMS MB95F104ANS MB95F104AJS MB95F106AMS MB95F106ANS MB95F106AJS MB95F108AMS MB95F108ANS MB95F108AJS Setting disabled Single-system clock mode MB95F104AMW MB95F104ANW MB95F104AJW MB95F106AMW MB95F106ANW MB95F106AJW MB95F108AMW MB95F108ANW MB95F108AJW Setting disabled Dual-system clock mode
Part number No.
MB95108AM
MB95FV100D-103
Specifying procedure Clock mode select * Single-system clock mode * Dual-system clock mode Low voltage detection reset* * With low voltage detection reset * Without low voltage detection reset Clock supervisor* * With clock supervisor * Without clock supervisor
Specify when ordering MASK Selectable
Setting disabled Changing by the switch on MCU board
1
2
Specify when ordering MASK
Specified by part number
Specified by part number
Changing by the switch on MCU board
3
Specify when ordering MASK
Specified by part number
Specified by part number
Changing by the switch on MCU board MCU board switch set as following ; * With supervisor : Without reset output * Without supervisor : With reset output Fixed to oscillation stabilization wait time of (214-2) /FCH
4
Reset output* * With reset output * Without reset output
Specify when ordering MASK
Specified by part number
Specified by part number
5
Oscillation stabilization wait time
Fixed to Fixed to Fixed to oscillation oscillation oscillation stabilization wait stabilization wait stabilization wait time of time of time of (214-2) /FCH (214-2) /FCH (214-2) /FCH
* : Refer to table below about clock mode select, low voltage detection reset, clock supervisor select and reset output.
66
MB95100AM Series
Part number
Clock mode select
Low voltage detection reset No Yes Yes No
Clock supervisor No No Yes No No Yes No No Yes No No Yes No No Yes No No Yes No No Yes No No Yes No No Yes No No Yes
Reset output Yes Yes No Yes Yes No Yes Yes No Yes Yes No Yes Yes No Yes Yes No Yes Yes No Yes Yes No Yes Yes No Yes Yes No
Single-system MB95108AM Dual-system MB95F104AMS MB95F104ANS MB95F104AJS MB95F106AMS MB95F106ANS MB95F106AJS MB95F108AMS MB95F108ANS MB95F108AJS MB95F104AMW MB95F104ANW MB95F104AJW MB95F106AMW MB95F106ANW MB95F106AJW MB95F108AMW MB95F108ANW MB95F108AJW Single-system MB95FV100D-103 Dual-system Dual-system Single-system
Yes Yes No Yes Yes No Yes Yes No Yes Yes No Yes Yes No Yes Yes No Yes Yes No Yes Yes No Yes Yes
67
MB95100AM Series
ORDERING INFORMATION
Part number MB95108AMPFV MB95F104AMSPFV/F104ANSPFV/F104AJSPFV MB95F104AMWPFV/F104ANWPFV/F104AJWPFV MB95F106AMSPFV/F106ANSPFV/F106AJSPFV MB95F106AMWPFV/F106ANWPFV/F106AJWPFV MB95F108AMSPFV/F108ANSPFV/F108AJSPFV MB95F108AMWPFV/F108ANWPFV/F108AJWPFV MB95108AMPFM MB95F104AMSPFM/F104ANSPFM/F104AJSPFM MB95F104AMWPFM/F104ANWPFM/F104AJWPFM MB95F106AMSPFM/F106ANSPFM/F106AJSPFM MB95F106AMWPFM/F106ANWPFM/F106AJWPFM MB95F108AMSPFM/F108ANSPFM/F108AJSPFM MB95F108AMWPFM/F108ANWPFM/F108AJWPFM MB2146-303 (MB95FV100D-103PBT) Package
64-pin plastic LQFP (FPT-64P-M03)
64-pin plastic LQFP (FPT-64P-M09)
(
MCU board 224-pin plastic PFBGA (BGA-224P-M08)
)
68
MB95100AM Series
PACKAGE DIMENSIONS
64-pin plastic LQFP Lead pitch Package width x package length Lead shape Sealing method Mounting height Weight 0.50 mm 10.0 x 10.0 mm Gullwing Plastic mold 1.70 mm MAX 0.32g P-LFQFP64-10x10-0.50
(FPT-64P-M03)
Code (Reference)
64-pin plastic LQFP (FPT-64P-M03)
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
12.000.20(.472.008)SQ
* 10.000.10(.394.004)SQ
48 33
0.1450.055 (.006.002)
49
32
Details of "A" part 0.08(.003) 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
INDEX
64 17
0~8 "A" 0.500.20 (.020.008) 0.600.15 (.024.006)
0.100.10 (.004.004) (Stand off)
0.25(.010)
LEAD No.
1
16
0.50(.020)
0.200.05 (.008.002)
0.08(.003)
M
C
2003 FUJITSU LIMITED F64009S-c-5-8
Dimensions in mm (inches). Note: The values in parentheses are reference values
Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html (Continued)
69
MB95100AM Series
(Continued)
64-pin plastic LQFP Lead pitch Package width x package length Lead shape Sealing method Mounting height Code (Reference) 0.65 mm 12 x 12 mm Gullwing Plastic mold 1.70 mm MAX P-LQFP64-12x12-0.65
(FPT-64P-M09)
64-pin plastic LQFP (FPT-64P-M09)
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
14.000.20(.551.008)SQ
* 12.000.10(.472.004)SQ
48 33
0.1450.055 (.0057.0022)
49
32
0.10(.004) Details of "A" part 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
0.25(.010) INDEX 0~8
64 17
1
16
"A"
0.65(.026)
0.320.05 (.013.002)
0.500.20 (.020.008) 0.600.15 (.024.006)
0.100.10 (.004.004) (Stand off)
0.13(.005)
M
C
2003 FUJITSU LIMITED F64018S-c-3-5
Dimensions in mm (inches). Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
70
MB95100AM Series
MAIN CHANGES IN THIS EDITION
Page Section Change Results Added the part numbers. ( MB95F104AJS/MB95F104AJW MB95F106AJS/MB95F106AJW MB95F108AJS/MB95F108AJW) Added the description "Clock supervisor" in the section "Option".
4
PRODUCT LINEUP
18 31
PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL Inserted "* Programming Method". PROGRAMMER I/O MAP Added the address 0FEAH. "Verified the Min value in the section of "Other than MB95FV100D-103", "In normal operating" of "Power supply voltage"; 2.45 2.42.
35
2. Recommended Operating Conditions
Verified the value in *1; 2.9 V 2.88 V. Moved "H" level input voltage and "L" level input voltage to the section "3. DC Characteristics". Added the pin name at the "Pin name" in the section of VIHA, "H" level input voltage.
36 3. DC Characteristics 39
Added the pin name at the "Pin name" in the section of VILA, "L" level input voltage. Deleted the line of "FCH = 16 MHz" in the section "ICTS" of Power supply current. Changed in the table; VCC = 2.5 V to 5.5 V VCC = 2.42 V to 5.5 V. Changed the Max value on the third column of the clock frequency; 16.25 10.00 Verified the diagram of Main PLL operation frequency range. Changed the release voltage: 2.55 2.52 (Min value) 2.85 2.88 (Max value) Changed the detection voltage: 2.45 2.42 (Min value) 2.75 2.78 (Max value)
40
4. AC Characteristics (1) Clock Timing
45
4. AC Characteristics (2) Source Clock/Machine Clock
59
(9) Low Voltage Detection
71
MB95100AM Series
The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited Business Promotion Dept.
F0611

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